Simulink Design Verifier 1.5

Test Generation

Simulink Design Verifier analyzes the algorithms and logic in your Simulink and Stateflow models to generate test harness models. Harness models contain sets of test cases within a Signal Builder block. Groups in the Signal Builder block contain the input data values for test cases and enable convenient viewing and elaboration. Each test case indicates the specific test objectives that it satisfies.

Model coverage test objectives include MC/DC coverage, which is required by safety critical standards, such as DO-178B. User-defined objectives are created using Test Objective blocks from the Simulink Design Verifier library. You can fine-tune the analysis by adding Test Condition blocks from the Simulink Design Verifier library to your model to constrain signal values in the generated tests.

With test generation, Simulink Design Verifier highlights and reports objectives that it proves cannot be satisfied. These objectives typically indicate design flaws that require investigation.