Verify Design Through Model Testing
Verification, Validation (V&V), and Test Workflow Diagram. Enlarge image
Develop model tests as you design
Writing effective tests to verify designs requires a significant amount of knowledge about the system being developed. Developing tests in parallel with design and development engages the tester early in the process and facilitates model V&V. This collaboration results in early design verification and significant reduction of cost and time required for fixing errors.
Simulink Verification and Validation aids model verification by building unit tests and creating model test harnesses. Simulink Design Verifier can generate tests directly from models. And SystemTest stores TEST-files separately from Simulink MDL-files or M-files, so you can iterate simulation and testing independently of the model.
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Run the same tests in simulation and in the lab
Reuse of tests is a key value of Model-Based Design. Hardware testing is done almost everywhere; however, it is often disconnected from testing in simulation. By running the same tests on your model that you run in the lab, you know exactly how the design should perform in the lab. If testing creates an unexpected result, reusing the tests makes it quick and easy to recreate the test in simulation, where it is easier to iterate the design and fix the problem.
SystemTest provides a software framework for automating tests on Simulink models or MATLAB algorithms. It also enables easy import or export of tests in other formats, such as Excel or CSV. xPC Target enables hardware-in-the-loop testing in the lab.
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Verify design by exhaustive testing for variability in simulation
Time and expense often limit the amount of variability you can test. By performing model V&V tests in a simulation environment, you can simulate different test cases much faster and, if the processing power is available, in parallel. Exploring the entire parameter space in simulation can narrow down tests to those that are critical to run on real-time targets or, later, real-world hardware.
SystemTest supports Monte Carlo simulations, which exercise a model over large, randomized parameter spaces. Simulink Verification and Validation enables model coverage, a measure of how much a model has been tested.
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Test on real-time targets before testing on real hardware
Many control algorithms are developed in an ideal, simulated realm and never encompass all the complexities that exist in the real world, where many of these algorithms will operate. Real-time model and algorithm testing allows immediate insight into real-world performance. Studying how a control algorithm performs in repeatable, controllable, real-time conditions allows understanding and refinement of the algorithm without endangering equipment and personnel.
xPC Target lets you reuse Simulink plant models and control algorithms and test them using a real-time kernel on inexpensive, high-performance open hardware architectures.
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Document design verification and model tests
The underlying principle in most quality standards is documentation—document your requirements; document your process; document your results. While documentation is often seen as tedious, many MathWorks tools enable automation of documentation activities.
Simulink Design Verifier, Simulink Verification and Validation and SystemTest enable automatic documentation by generating reports of model coverage, simulation, and test results. And Simulink Report Generator lets you create specific, customized reports.
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Assess Verification and Validation (V&V) Completeness
Trace your requirements to your models
By mapping requirements to models, you assure that all requirements are being met and that the model you built is addressing appropriate requirements. This mapping provides early validation of requirements, verification of your design model, and verification of your tests.
Simulink Verification and Validation provides the Requirements Management Interface to allow mapping of written requirements to Simulink or Stateflow models.
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Develop modeling standards and check for compliance
Every organization has standards or best practices. Formalizing the standards and incorporating standard checks into your model validation process is straightforward and can have a large impact by reducing the number of "silly" errors introduced early in the development process. Modeling standards can be as simple as verifying that all your inputs and outputs are connected to something and as complex as meeting industry standards, such as DO-178B or IEC 61508. The key is developing consistent checks and then driving compliance to them throughout the organization.
Simulink Verification and Validation enables you to write custom checks in the Simulink environment using the Model Advisor.
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Run model coverage
Using Simulink Verification and Validation for model coverage.
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Model coverage is a metric collected during simulation that provides information about model objects (blocks, states, and transitions) that were executed in simulation, and more importantly, it highlights those objects that have not yet been tested. Model coverage can be used to asses the completeness of the test harness and prompt for development of additional test cases that will exercise the untested portion of the model.
Simulink Verification and Validation enables collection of model coverage, as well as highlighting untested portions of your Simulink or Stateflow model. Simulink Design Verifier can generate tests to achieve 100% coverage.
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Use formal methods
Formal methods are mathematically rigorous procedures used to analyze all possible execution paths of a design and find examples of data that can cause functional problems or inconsistencies with functional requirements. With the help of formal methods, you can completely and exhaustively verify your designs. Verification using formal methods provides confidence that certain types of design problems and runtime errors cannot occur by design. Having this confidence is especially important for safety-critical applications.
Simulink Design Verifier enables analysis of Simulink and Stateflow models. It generates tests for complete model coverage, finds model elements that represent dead code, and proves design properties. Simulink Design Verifier is optimized for the discrete-time subset of Simulink and Stateflow typically used in embedded control applications. PolySpace code verifiers enable formal verification of source code. They prove the correctness of code and verify that it does not have any runtime errors.
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